Theo Ungerer
Project Coordinator
Theo Ungerer studied mathematics and computer science at the
Universities of Heidelberg and Zürich and at the Technical University
of Berlin. He received a Diploma in Mathematics at the Technical
University of Berlin in 1981, a Doctoral Degree at the University of
Augsburg in 1986, and a second Doctoral Degree (Habilitation) at the
University of Augsburg in 1992. Ungerer was scientific assistant at
the University of Augsburg (1982-89 and 1990-92), visiting assistant
professor at the University of California, Irvine (1989-90), professor
of computer architecture at the University of Jena (1992-1993) and the
Technical University of Karlsruhe (1993-2001). Since April 2001 he is
Chair of Systems and Networking at the University of Augsburg,
Germany. Since 2003 he is also scientific director of the Computing
Center of the University of Augsburg.
His current research interests are in the areas of embedded
processor architectures, embedded real-time systems, ubiquitous
systems, and organic computing. He is steering committee member and
German coordinator of the EC HiPEAC (High-performance Embedded
Architectures and Compilers) network of excellence and in the steering
committee of the Priority Program DFG SPP 1183 "Organic Computing" of
the German Research Foundation.
Homepage: http://www.informatik.uni-augsburg.de/en/chairs/sik/
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Francisco J. Cazorla
Francisco J. Cazorla is a senior researcher in the Barcelona
Supercomputing Center/Centro Nacional de Supercomputación
(BSC-CNS). He received his BS degree in 1999 by the University of Las
Palmas de Gran Canaria, and his MS degree in 2001 by the same
university (he was awarded best student record in Computer Science in
2001). He also has a PhD (2005) by the Universitat Politecnica de
Catalunya. He has been summer student intern for 5 months with IBM's
T.J. Watson in New York in 2004. His research area focuses on
multithreaded architectures for both high-performance and real-time
computing systems. He has co-authored over 20 papers in international
refereed conferences and journals. Francisco J. Cazorla heads the
research group on embedded real-time systems at BSC.
Homepage: http://personals.ac.upc.edu/fcazorla/
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Roberto Gioiosa
Roberto Gioiosa is currently a senior researcher at the BSC. He
received his MS degree in Computer Science Engineer in 2002 by the
University of Rome "Tor Vergata", Italy with Summa cum
Laude. He received his PhD Computer Science in May 2006 by the
University of Rome "Tor Vergata", Italy. He was graduated
student from April 2004 to June 2005 at the Los Alamos National
Laboratory (LANL), Los Alamos, New Mexico, US. From June 2005 to
August 2006 he was a researcher at the University of Rome "Tor
Vergata" where he worked for project, development and implementation
of hard real time, certified (DO178B) OS for embedded systems (Linux,
VxWorks).
Homepage: http://www.sprg.uniroma2.it/home/gioiosa/
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Marco Paolieri
Marco Paolieri obtained a Bachelor in Computer Engineering at School of
Engineering, University of Florence (Italy) in 2005. In 2004-05 he
was an exchange student at Tampere University of Technology (Finland) where
he worked also as research assistant at Institute of Signal Processing.
In 2007 he completed a Master of Science in Embedded Systems Design at
ALaRI - Advanced Learning and Research Institute - Faculty of
Informatics, University of Lugano (Switzerland). He is currently a PhD
Student at Computer Architecture Department at Barcelona
Supercomputing Center.
Homepage: http://personals.ac.upc.edu/paolieri//
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Eduardo Quiñones
Eduardo Quiñones received his MS degree in 2003 by the Universitat Politecnica de Catalunya. He is at the point of ending the PhD by the same university. His area of expertise is high performance compiler techniques, particuarly on Itanium platforms. He has also experience in hardware simulation methodologies.
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Pascal Sainrat
Pascal Sainrat received his Doctoral Degree in 1991 and his second
Doctoral Degree (habilitation) in 1998. After some years spent at
CNRS, Pascal Sainrat has joined Université de Toulouse in 2002 and is
currently the head of the TRACES team at IRIT (Institut de Recherche
en Informatique de Toulouse). His current research topics mainly
concern processor architecture and predictability of hardware
systems. He is a member of the steering committee and the CNRS
coordinator of the EC HiPEAC (High-performance Embedded Architectures
and Compilers) network of excellence.
Homepage: http://www.irit.fr/recherches/ARCHI/MARCH/rubrique.php3?id_rubrique=88
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Christine Rochange
Christine Rochange received her PhD at Université de
Toulouse in 1993. Since 1996, she is an assistant professor at
Université de Toulouse where she teaches computer science. She
is a member of the Institut de Recherche en Informatique de Toulouse
and her research interests include critical real-time systems and
computer architecture. Her current focus is on the timing
predictability of high-performance processors.
Homepage: http://www.irit.fr/recherches/ARCHI/MARCH/
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Hugues Cassé
Hugues Cassé has received his PhD degree in 2001 at
Université de Toulouse. After three years spent in the
industry, he joined, as an assistant professor, the TRACES team from
the Institut de Recherche en Informatique de Toulouse. He teaches
computer science and his research interests includes embedded and
real-time systems, static analyses and compiler implementation. He is
currently the leader of the OTAWA project.
Homepage: http://www.otawa.fr/
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Guillem Bernat (Rapita Systems Ltd.)
Rapita Systems Ltd. is a specialist in real-time systems analysis, its
innovative RapiTime product makes Rapita Systems the leader in measurement
based worst-case execution time analysis solutions. RapiTime provides a
practical performance analysis that works for complex embedded software
running on the latest generation of advanced microprocessors.
RapiTime is successfully used in the Avionics, Automotive and
Telecommunications markets. Recent work with BAE Systems on the
performance analysis of the mission computer of the Hawk aircraft has
earned Rapita one of the 2006 BAE Systems Chairman's awards.
Homepage: http://www.rapitasystems.com/
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Tomas Kratochvila
Tomas Kratochvila received his bachelor and master degree in Parallel and
Distributed Systems at the Masaryk University in Brno, 2005. He has been working
on formal verification of the hardware and software of multigigabit PC-based FPGA
router with completely open design. He researched and implemented automatic always
best connected seamless handover between wired and wireless networks in European Ambient
Networks research project in 2006 and 2007. He is familiar with real-time system designs,
wireless network prototyping and formal verification methods. He is currently with
Honeywell, Brno, Czech Republic as Platform Systems Technologist.
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Petr Novotny
Petr Novotny is a Program Manager in the Honeywell's Aerospace
Advanced Technology. He graduated in Electronic Engineering at Brno
(Czech Rep.) University of Technology in 1993, specialization of
control systems. Prior to Honeywell, Petr worked for 14 years as a
software engineer, software architect, project manager and head of R&D
department (wide portfolio of customers like Audi, Bayer, BMW,
Mercedes-Benz, Novartis, Roche). Petr has deep knowledge in the domain
of embedded real-time systems development since his employment by
Siemens in the period 2003-2007. He led international multi-site
projects focused on firmware for cell phones (Siemens Mobile,
Infineon/Comneon).
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Zlatko Petrov
Zlatko Petrov received his bachelor and master degree in Automation
and Control Systems at the Technical University of Varna, Bulgaria
in 2000. He has been involved in a modernization of man-portable
ground radar for aquisition and surveillance NR-100, where he has
dealt with reliable detection in heavy-tailed folliage clutter. He
has two IEEE conference papers on those problems.
In 2004/2005 he has been guest researcher in Aalborg University,
Denmark, where he has worked on pyramidal transforms.
In 2007, he completed a Master of Advanced Studies in Embedded Systems
Design at ALaRI (Advanced Learning and Research Institute),
University of Lugano, Switzerland.
He is currently with Honeywell, Brno, Czech Republic as Platform
System Technologist.
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